1. Field of the Invention
The present invention relates to a technique to reduce the power consumption of a serial data transfer apparatus which transmits/receives to/from a destination apparatus via a serial bus.
2. Description of Related Art
High-speed serial transfer interfaces, such as serial ATA (SATA), SAS (Serial Attached SCSI), PCI Express, and USB3.0, are used for various communication devices.
FIG. 14 is FIG. 1 of Japanese Unexamined Patent Application Publication No. 2007-233993, illustrating the layer structure of the SATA transfer interface disclosed in Japanese Unexamined Patent Application Publication No. 2007-233993.
It is defined that the layer structure of SATA is divided into a physical layer, a link layer, a transport layer, and an application layer based on the OSI reference model. The processes of the physical layer, the link layer, and the transport layer are realized by a physical layer circuit (PHY controller), a link controller, and a transport controller which are provided to a host and a device side. The process of the application layer is realized by software, a buffer memory, and a DMA (Direct Memory Access) engine etc., which are provided to both the host and the device side.
As shown in FIG. 14, the SATA transfer interface includes a physical layer circuit 100, a link controller 50, and a transport controller 10.
The transport controller 10 performs the process of the transport layer. In response to a transmission request of FIS (Frame Information Structure), which is to be transmission data, from an upper layer (the application layer), the transport controller 10 transmits data to the link layer. When the transport controller 50 receives FIS, which is reception data, from the link controller 50, the transport controller 10 notifies the reception result to the upper layer.
The physical layer circuit 100 performs the process of the physical layer, which is to carry out a parallel-to-serial conversion to the data received from the link controller 50 by a transmitter 110 and output it to a SATA bus. When receiving data by a receiver 120 via a SATA bus, the physical layer circuit 100 performs a serial-to-parallel conversion to the received data and outputs it to the link controller 50.
The link controller 50 performs the process of the link layer. In order to transmit the transmission data FIS from the transport controller 10, the link controller 50 adds a CRC generation result, performs a scrambling process, an 8b/10b encoding, and adds primitives such as SOF (Start of Frame) and EOF (End of Frame), to output the data to the physical layer circuit 100.
In SATA, a CONT primitive is prepared to avoid EMI (Electro Magnetic Interference) caused by same and consecutive control codes. When a receiving side receives the CONT primitive, reception data following the CONT primitive is ignored until another effective primitive is received. Therefore, in an idle period when FIS is not transferred, a sending side uses the CONT primitive to transmit scramble data, so as to reduce EMI.
Thus the link controller 50 also has a function to generate scramble data for the idle period, and continues to transmit the scramble data following the CONT primitive in the idle period until another effective primitive is transmitted.
For the data received from the physical layer circuit 100, the link controller 50 analyzes the primitives, performs an 8b/10h decoding, a descrambling process, and a CRC check, so as to obtain FIS, which is reception data, and a CRC check result, and outputs them to the transport controller 10,
As shown in FIG. 14, the link controller 50 is divided into a Tx block, which is responsible for transmission, and an Rx block, which is responsible for reception.
The Tx block includes a pattern generator 52, a scrambler 54, a selector 61, a CRC calculation unit 58, a selector 62, a data scrambler 56, a selector 63, and an 8b/10b encoder 60. The Tx block is responsible for the abovementioned transmission process by the link controller 50. Among these functional blocks, the data scrambler 56 performs scrambling process to FIS and CRC when transmitting the FIS. The scrambler 54 generates scramble data following the CONT primitive in the idle period. The SATA standard defines to generate the scramble data by a linear feedback shift register (LFSR) using a generator polynomial.
The Rx block of the link controller 50 includes an 8b/10b decoder 74, a data descrambler 70, and a CRC calculation unit 72. The Rx block is responsible for the abovementioned reception process by the link controller 50. When receiving a CONT primitive, the Rx block discards the scramble data following the CONT primitive until another effective primitive is received.
Not limited to SATA, but many of the abovementioned high-speed serial interfaces are defined to continue transmitting idle data like the scramble data following the CONT primitive in the idle period. In such serial transfer interfaces, the functional blocks (such as the scrambler 54 and the 8b/10b encoder 60 in FIG. 14) for generating idle data must keep operating during the idle period as well.
Therefore, such high-speed serial transfer interfaces consumes power even in the idle period. For the serial transfer interfaces such as PCI Express which is targeted for personal computers, power saving is not strongly requested. Therefore, it is not an issue even if idle data is output during the idle period. However, for mobile information devices such as mobile phones, the amount of power consumption is a major issue that concerns the existence of the product and various attempts have been made to save power in the idle period.
Japanese Unexamined Patent Application Publication No. 2005-260360 discloses a data transfer apparatus that achieves to save power in the idle period. In this data transfer apparatus, in the idle period, an encoder circuit stops operation, and a transmitter in a physical layer circuit continues to output idle signals with its logical level fixed to a first logical level to a serial bus for a predetermined number of bits or more, as signals to indicate the idle state.
The data transfer apparatus prevents the encoder circuit from consuming power in the idle period and thus attempts to save power.